1. Field of the Invention
This invention relates to the use of a FLASH EPROM in a single chip embedded microcontroller (smart card). More particularly the invention relates to an error check and correction (ECC) circuit to prolong the effective endurance of read/write cycles of the FLASH EPROM and hence allow its use in smart cards.
2. Description of the Related Art
A basic contact smart card functions in much the same way that a personal computer (PC) does. Its integrated circuit (IC) has a central processing unit (CPU) or microcontroller, that controls all processes and transactions that take place on the card.
Smart card Integrated Circuits (ICs) require non-volatile storage, to hold code and changed data. Both types of storage are implemented using different technologies. Byte erasable EEPROM is used for data storage and masked ROM or one time programmable ROM is used for code storage. This results in a complex manufacturing process and a large and inflexible IC. FIG. 1 shows a typical prior art smart card having EEPROM for data storage.
EEPROM (Erasable electrically programmable read only memory) is a flexible and robust form of nonvolatile memory. Data stored on it remains there even when there is no power supply, and the data can be changed quickly and easily, although not as quickly as RAM. For these reasons, EEPROM can store a wide variety of data types, but generally stores application-specific data, personal-identification (ID) and customized feature information, and, in cases of stored-value applications, the stored value itself.
Smart cards typically need an endurance of 100,000 read/write cycles when reading/writing is byte by byte to the microcontroller on the card. Endurance is the number of read/write cycles a memory can undergo before losing the ability to store data without errors.
EEPROMs meet this requirement since the number of read/write cycles available to an EEPROM through its life cycle is approximately 100,000. EEPROM memories also meet the requirement of altering the content of the memory by single bytes (herein intended to constitute a unit of information composed of a certain number of bits, for example 8, 16, 32, etc.) without having to reprogram blocks of bytes of the memory as with the case EPROM memories. The EEPROM is able to erase certain selected cells while leaving unchanged the information content of other cells.
Bytewise erasability of EEPROM memories is achieved with a penalty in terms of compactness of the matrix of memory cells. Overall the cells are from three to four times larger than an EPROM cell, because they require a select transistor associated with each cell. In addition, the fabrication process of an EEPROM memory is notably much more complex than that of an EPROM process, and the EEPROM memory requires relatively more complex overhead circuitry as well as the integration of voltage multipliers. A schematic cross section of an EEPROM cell is shown in FIG. 2.
It would be desirable to have a non-volatile erasable PROM memory for the microcontroller in a smart card that is smaller than EEPROM but would have an endurance of 100,000 read/write cycles needed by a smart card.